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343 tm march 1997 82C89 cmos bus arbiter features ? pin compatible with bipolar 8289 ? performance compatible with: - 80c86/80c88 . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8mhz) ? provides multi-master system bus control and arbitration ? provides simple interface with 82c88/8288 bus controller ? synchronizes 80c86/8086, 80c88/8088 processors with multi-master bus ? bipolar drive capability ? four operating modes for flexible system configura- tion ? low power operation - iccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 a (max) - iccop . . . . . . . . . . . . . . . . . . . . . . . . . 1ma/mhz (max) ? operating temperature ranges - c82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c - i82C89 . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c - m82C89 . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c description the intersil 82C89 bus arbiter is manufactured using a self- aligned silicon gate cmos process (scaled saji iv). this cir- cuit, along with the 82c88 bus controller, provides full bus arbi- tration and control for multi-processor systems. the 82C89 is typically used in medium to large 80c86 or 80c88 systems where access to the bus by several processors must be coordi- nated. the 82C89 also provides high output current and capac- itive drive to eliminate the need for additional bus buffering. static cmos circuit design insures low operating power. the advanced intersil saji cmos process results in perfor- mance equal to or greater than existing equivalent products at a significant power savings. pinouts 82C89 (cerdip) top view 82C89 (plcc, clcc) top view ordering information part number package temperature range pkg. no. cp82C89 20 ld pdip 0 o c to +70 o ce20.3 ip82C89 -40 o c to +85 o ce20.3 cs82C89 20 ld plcc 0 o c to +70 o cn20.35 is82C89 -40 o c to +85 o cn20.35 cd82C89 20 ld cerdip 0 o c to +70 o cf20.3 id82C89 -40 o c to +85 o cf20.3 md82C89/b -55 o c to +125 o cf20.3 5962-8552801ra smd# f20.3 mr82C89/b 20 pad clcc -55 o c to +125 o cj20.a 5962-85528012a smd# j20.a 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 v cc clk anyrqst busy cbrq aen crqlck lock s0 s1 gnd resb iob s2 bclk init breq bpro bprn sysb/resb 4 5 6 7 8 9101112 13 3212019 15 14 18 17 16 bclk resb init breq bpro gnd aen cbrq busy bprn v cc iob s1 lock crqlck clk anyrqst s0 sysb/ resb s2 fn2980.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
344 functional diagram pin description pin symbol number type description v cc 20 v cc : the +5v power supply pin. a 0.1 f capacitor between pins 10 and 20 is recommended for decoupling. gnd 10 ground. s0 , s1 , s2 1, 18-19 i status input pins: the status input pins from an 80c86, 80c88 or 8089 processor. the 82C89 decodes these pins to initiate bus request and surrender actions. (see table 1). clk 17 i clock: from the 82c84a or 82c85 clock chip and serves to establish when bus arbiter actions are initiated. lock 16 i lock: a processor generated signal which when activated (low) prevents the arbiter from surren- dering the multi-master system bus to any other bus arbiter, regardless of its priority. crqlck 15 i common request lock: an active low signal which prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter requesting the bus through the cbrq input pin. resb 4 i resident bus: a strapping option to configure the arbiter to operate in systems having both a multi-master system bus and a resident bus. strapped high, the multi-master system bus is re- quested or surrendered as a function of the sysb/resb input pin. strapped low, the sysb/resb input is ignored. anyrqst 14 i any request: a strapping option which permits the multi-master system bus to be surrendered to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible). when anyrqst is strapped low, the bus is surrendered according to table a in design informa- tion. if anyrqst is strapped high and cbrq is activated, the bus is surrendered at the end of the present bus cycle. strapping cbrq low and anyrqst high forces the 82C89 arbiter to sur- render the multi-master system bus after each transfer cycle. note that when surrender occurs breq is driven false (high). control arbitration multibus interface local bus interface +5v gnd control/ strapping options 80c86/ 80c88 status command signals multibus tm system signals multibus tm is an intel corp. trademark bprn sysb/ resb init bclk breq bpro busy cbrq aen clk resb anyrqst lock s 1 iob crqlck s 0 s 2 status decoder 82C89
345 iob 2 i io bus: a strapping option which configures the 82C89 arbiter to operate in systems having both an io bus (peripheral bus) and a multi-master system bus. the arbiter requests and surrenders the use of the multi-master system bus as a function of the status line, s2 . the multi-master sys- tem bus is permitted to be surrendered while the processor is performing io commands and is requested whenever the processor performs a memory command. interrupt cycles are assumed as coming from the peripheral bus and are treated as an io command. aen 13 o address enable: the output of the 82C89 arbiter to the processor?s address latches, to the 82c88 bus controller and 82c84a or 82c85 clock generator. aen serves to instruct the bus controller and address latches when to three-state their output drivers. init 6 i initialize: an active low multi-master system bus input signal used to reset all the bus arbiters on the multi-master system bus. after initialization, no arbiters have the use of the multi-master system bus. sysb/resb 3 i system bus/resident bus: an input signal when the arbiter is configured in the system/res- ident mode (resb is strapped high) which determines when the multi-master system bus is re- quested and multi-master system bus surrendering is permitted. the signal is intended to originate from a form of address-mapping circuitry, such as a decoder or prom attached to the resident address bus. signal transitions and glitches are permitted on this pin from 1 of t4 to 1 of t2 of the processor cycle. during the period from 1 of t2 to 1 of t4, only clean transitions are permit- ted on this pin (no glitches). if a glitch occurs, the arbiter may capture or miss it, and the multi- master system bus may be requested or surrendered, depending upon the state of the glitch. the arbiter requests the multi-master system bus in the system/resident mode when the state of the sysb/resb pin is high and permits the bus to be surrendered when this pin is low. cbrq 12 i/o common bus request: an input signal which instructs the arbiter if there are any other arbi- ters of lower priority requesting the use of the multi-master system bus. the cbrq pins (open-drain output) of all the 82C89 bus arbiters which surrender to the multi- master system bus upon request are connected together. the bus arbiter running the current transfer cycle will not itself pull the cbrq line low. any other arbiter connected to the cdrq line can request the multi-master system bus. the arbiter presently running the current transfer cycle drops its breq signal and surrenders the bus whenever the proper surrender conditions exist. strapping cbrq low and anyrqst high allows the multi-mas- ter system bus to be surrendered after each transfer cycle. see the pin definition of anyrqst. bclk 5 i bus clock: the multi-master system bus clock to which all multi-master system bus interface signals are synchronized. breq 7 o bus request: an active low output signal in the parallel priority resolving scheme which the arbiter activates to request the use of the multi-master system bus. bprn 9 i bus priority in: the active low signal returned to the arbiter to instruct it that it may acquire the multi-master system bus on the next falling edge of bclk . bprn active indicates to the arbiter that it is the highest priority requesting arbiter presently on the bus. the loss of bprn instructs the ar- biter that it has lost priority to a higher priority arbiter. bpro 8 o bus priority out: an active low output signal used in the serial priority resolving scheme where bpr o is daisy-chained to bprn of the next lower priority arbiter. busy 11 i/o busy: an active low open-drain multi-master system bus interface signal used to instruct all the arbiters on the bus when the multi-master system bus is available. when the multi-master system bus is available the highest requesting arbiter (determined by bprn ) seizes the bus and pulls busy low to keep other arbiters off of the bus. when the arbiter is done with the bus, it releases the busy signal, permitting it to go high and thereby allowing another arbiter to acquire the multi- master system bus. pin description (continued) pin symbol number type description 82C89
346 functional description the 82C89 bus arbiter operates in conjunction with the 82c88 bus controller to interface 80c86, 80c88 processors to a multi-master system bus (both the 80c86 and 80c88 are configured in their max mode). the processor is unaware of the arbiter?s existence and issues commands as though it has exclusive use of the system bus. if the proces- sor does not have the use of the multi-master system bus, the arbiter prevents the bus controller (82c88), the data transceivers and the address latches from accessing the system bus (e.g. all bus driver outputs are forced into the high impedance state). since the command sequence was not issued by the 82c88, the system bus will appear as ?not ready? and the processor will enter wait states. the proces- sor will remain in wait until the bus arbiter acquires the use of the multi-master system bus whereupon the arbiter will allow the bus controller, the data transceivers, and the address latches to access the system. typically, once the command has been issued and a data transfer has taken place, a transfer acknowledge (xack) is returned to the pro- cessor to indicate ?ready? from the accessed slave device. the processor then completes its transfer cycle. thus the arbiter serves to multiplex a processor (or bus master) onto a multi-master system bus and avoid contention problems between bus masters. arbitration between bus masters in general, higher priority masters obtain the bus when a lower priority master completes its present transfer cycle. lower priority bus masters obtain the bus when a higher pri- ority master is not accessing the system bus. a strapping option (anyrqst) is provided to allow the arbiter to surren- der the bus to a lower priority master as though it were a master of higher priority. if there are no other bus masters requesting the bus, the arbiter maintains the bus so long as its processor has not entered the halt state. the arbiter will not voluntarily surrender the system bus and has to be forced off by another master?s bus request, the halt state being the only exception. additional strapping options permit other modes of operation wherein the multi-master system bus is surrendered or requested under different sets of conditions. priority resolving techniques since there can be many bus masters on a multi-master sys- tem bus, some means of resolving priority between bus mas- ters simultaneously requesting the bus must be provided. the 82C89 bus arbiter provides several resolving tech- niques. all the techniques are based on a priority concept that at a given time one bus master will have priority above all the rest. there are provisions for using parallel priority resolving techniques, serial priority resolving techniques, and rotating priority techniques. parallel priority resolving the parallel priority resolving technique uses a separate bus request line breq for each arbiter on the multi-master sys- tem bus, see figure 1. each breq line enters into a priority encoder which generates the binary address of the highest priority breq line which is active. the binary address is decoded by a decoder to select the corresponding bprn (bus priority in) line to be returned to the highest priority requesting arbiter. the arbiter receiving priority (bprn true) then allows its associated bus master onto the multi-master system bus as soon as it becomes available (i.e., the bus is no longer busy). when one bus arbiter gains priority over another arbiter it cannot immediately seize the bus, it must wait until the present bus transaction is complete. upon completing its transaction the present bus occupant recog- nizes that it no longer has priority and surrenders the bus by releasing busy . busy is an active low ?or? tied signal line which goes to every bus arbiter on the system bus. when busy goes inactive (high), the arbiter which presently has bus priority (bprn true) then seizes the bus and pulls busy low to keep other arbiters off of the bus. see waveform tim- ing diagram, figure 2. note that all multimaster system bus transactions are synchronized to the bus clock (bclk ). this allows the parallel priority resolving circuitry or any other pri- ority resolving scheme employed to settle. figure 1. parallel priority resolving technique figure 2. higher priority arbiter obtaining the bus from a lower priority arbiter notes: 1. higher priority bus arbiter requests the multi-master system bus. 2. attains priority. 3. lower priority bus arbiter releases busy . 4. higher priority bus arbiter then acquires the bus and pulls busy down. bus arbiter 1 bus arbiter 2 bus arbiter 3 bus arbiter 4 74hc148 priority encoder 74hc138 3 to 8 encoder ? ? ? ? ?? ?? ? ? ? ? breq bprn breq bprn breq bprn breq bprn busy cbrq bclk breq bprn busy 1 2 3 4 82C89
347 serial priority resolving the serial priority resolving technique eliminates the need for the priority encoder-decoder arrangement by daisychain- ing the bus arbiters together, connecting the higher priority bus arbiter?s bpro (bus priority out) output to the bprn of the next lower priority. see figure 3. rotating priority resolving the rotating priority resolving technique is similar to that of the parallel priority resolving technique except that priority is dynamically re-assigned. the priority encoder is replaced by a more complex circuit which rotates priority between requesting arbiters thus allowing each arbiter an equal chance to use the multi-master system bus, over time. which priority resolving technique to use there are advantages and disadvantages for each of the techniques described above. the rotating priority resolving technique requires substantial external logic to implement while the serial technique uses no external logic but can accommodate only a limited number of bus arbiters before the daisy-chain propagation delay exceeds the multimaster?s sys- tem bus clock (bclk ). the parallel priority resolving tech- nique is in general a good compromise between the other two techniques. it allows for many arbiters to be present on the bus while not requiring too much logic to implement. 82C89 modes of operation there are two types of processors for which the 82C89 will provide support: an input/output processor (i.e. an nmos 8089 iop) and the 80c86, 80c88. consequently, there are two basic operating modes in the 82C89 bus arbiter. one, the iob (i/o peripheral bus) mode, permits the processor access to both an i/o peripheral bus and a multi-master sys- tem bus. the second, the resb (resident bus mode), per- mits the processor to communicate over both a resident bus and a multi-master system bus. an i/o peripheral bus is a bus where all devices on that bus, including memory, are treated as i/o devices and are addressed by i/o commands. all memory commands are directed to another bus, the multi-master system bus. a resident bus can issue both memory and i/o commands, but it is a distinct and separate bus from the multi-master system bus. the distinction is that the resident bus has only one master, providing full avail- ability and being dedicated to that one master. the iob strapping option configures the 82C89 bus arbiter into the iob mode and the strapping option resb config- ures it into the resb mode. it might be noted at this point that if both strapping options are strapped false, the arbiter interfaces the processor to a multi-master system bus only (see figure 4). with both options strapped true, the arbiter interfaces the processor to a multi-master system bus, a resident bus, and an i/o bus. in the iob mode, the processor communicates and controls a host of peripherals over the peripheral bus. when the i/o processor needs to communicate with system memory, it does so over the system memory bus. figure 5 shows a possible i/o processor system configuration. the 80c86 and 80c88 processors can communicate with a resident bus and a multi-master system bus. two bus con- trollers and only one bus arbiter would be needed in such a configuration as shown in figure 6. in such a system config- uration the processor would have access to memory and peripherals of both busses. memory mapping techniques are applied to select which bus is to be accessed. the sysb/resb input on the arbiter serves to instruct the arbiter as to whether or not the system bus is to be accessed. the signal connected to sysb/resb also enables or disables commands from one of the bus controllers. a summary of the modes that the 82C89 has, along with its response to its status lines inputs, is shown in table 1. bus arbiter 1 bus arbiter 2 bus arbiter 3 bus arbiter 4 ? ? ? ? bprn busy cbrq ? ? bpro bpro bpro bpro bprn bprn bprn figure 3. serial priority resolving note: the number of arbiters that may be daisy-chained together in the serial priority resolving scheme is a function of bclk and the propagation delay from arbiter to arbiter. normally, at 10mhz only 3 arbiters may be daisychained. 82C89
348 figure 4. typical medium complexity cpu system 82c84a/85 clock ready clk x1 rdy2 aen2 rdy1 aen1 x2 generator 82C89 bus clk s0 -s2 anyrqst iob resb arbiter aen 82c88 bus clk ale aen iob dt/r controller den address latch oe stb 82c82/ 82c83h (2 or 3) transceiver 82c86h/ oe dt/r (2) 82c87h v cc processor local bus status (s0 , s1 , s2 ) xcvr disable v cc xack multi-master system bus multi-master control bus multi-master system command bus multi-master system address bus multi-master system data bus multi-master system bus 80c86 cpu ad0-ad15 a16-a19 ready clk s0 s1 s2 82C89
349 figure 5. typical medium complexity iob system multi-master 8089 iop ad0-ad15 a16-a19 ready clk s0 s2 ready clk aen1 rdy1 aen2 82c84a/85 iob aen 82C89 clk s0 -s2 anyrqst 82c88 bus aen clk ale pden address latch oe stb 82c82/ 82c83h (2 or 3) clock rdy2 status (s0 , s1 , s2 ) resb bus arbiter controller den dt/r iob address latch oe stb 82c82/ 82c83h (2 or 3) transceiver oe t 82c86h/ 82c87h (2) oe t transceiver 82c86h/ 82c87h (2) xack system bus multi-master control bus multi-master command bus multi-master address bus multi-master data bus xcvr disable v cc i/o data bus i/o address bus i/o command bus system system system multi-master system bus i/o bus xack(i/o bus) processor local bus v cc 82C89
350 figure 6. 82C89 bus arbiter shown in system - resident bus configuration note: by adding another 82C89 arbiter and connecting its aen to the 82c88 whose aen is presently grounded, the processor could have access to two multi-master buses. transceiver toe 82c86h/ 82c87h (2) iob aen 82C89 s0 s2 clk anyrqst bus arbiter 82c84a/85 clock rdy2 ready aen2 rdy1 clk 80c86 cpu ready s0 -s2 ad0-ad15 a16-a19 clk aen1 s1 sysb/ resb resb den 82c88 clk s0 -s2 iob ale dt/r addr latch oe stb 82c82/ 82c83h (2 or 3) addr latch oe stb 82c82/ 82c83h (2 or 3) transceiver oe t 82c86h/ 82c87h (2) den 82c88 clk s0 -s2 ale dt/r aen prom or decoder or cmos hpl cen status aen cen v cc xack multi master system bus multi master system bus control multi master system command bus multi master system address bus multi master system data bus xack resident bus resident command bus resident address bus resident data bus resident bus multi master system bus (note) 82C89
351 table 1. summary of 82C89 modes, requesting and relinquishing the multi-master system bus single lines from 80c86 or 80c88 or 8088 iob mode only iob = low resb = low resb mode only io b = high, resb = high iob mode resb mode iob = low, resb = high single bus mode iob = high resb = low s2 s1 s0 sysb/resb = high sysb/resb = low sysb/resb = high sysb/resb = low i/o commands 0 0 0 0 0 1 0 1 0 x x x ? ? ? x x x x x x x x x ? ? ? halt011xxxxx x memory commands 1 1 1 0 0 1 0 1 0? ? ? ? ? ? ? x x x ? ? ? x x x ? ? ? idle111xxxxx x notes: 1. x = multi-master system bus is allowed to be surrendered. 2. ? = multi-master system bus is requested. mode pin strapping multi-master system bus requested** surrendered* single bus multi-master mode iob = high resb = low whenever the processor?s status lines go active hlt + ti ? cbrq + hpbrq ? resb mode only iob = high resb = high sysb/resb + high ? active status (sysb/resb = low + ti) ? cbrq + hlt + hpbrq iob mode only iob = low resb = low memory commands (i/o status + ti) ? cbrq + hlt + hpbrq iob mode resb mode iob = low resb = high (memory command) ? (sysb/resb = high) (i/o status commands) + sysb/resb = low) ? cbrq + hpbrq + hlt notes: *lock prevents surrender of bus to any other arbiter, crqlck prevents surrender of bus to any lower priority arbiter. ** except for halt and passive or idle status. ? hpbrq, higher priority bus request or bprn = 1. 1. io b active low. 2. resb active high. 3. + is read as ?or? and ? as ?and? 4. ti = processor idle status s2 , s1 , s0 = 111 5. hlt = processor halt status s2 , s1 , s0 = 011 82C89
352 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range c82C89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to +70 o c i82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c m82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c thermal resistance ja ( o c/w) jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 80 20 clcc package . . . . . . . . . . . . . . . . . . 90 24 pdip package . . . . . . . . . . . . . . . . . . . 75 n/a plcc package . . . . . . . . . . . . . . . . . . 75 n/a storage temperature range . . . . . . . . . . . . . . . . .-65 o c to +150 o c maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . +300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. dc electrical specifications v cc = 5.0v 10%; t a = 0 o c to +70 o c (c82C89); t a = -40 o c to +85 o c (i82C89); t a = -55 o c to +125 o c (m82C89) symbol parameter min max units test conditions v ih logical one input voltage 2.0 2.2 - - v v c82C89, i82C89 m82C89, note 1 v il logical zero input voltage - 0.8 v note 1 vihc clk logical one input voltage 0.7 vcc - v vilc clk logical zero input voltage - 0.2 vcc v v ol output low voltage busy , cbrq aen bpro , breq - - - 0.45 0.45 0.45 v v v i ol = 20ma i ol = 16ma i ol = 8ma voh1 output high voltage busy , cbrq open-drain voh2 output high voltage all other outputs 3.0 v cc -0.4 -v v i oh = -2.5ma i oh = -100 a ii input leakage current -1.0 1.0 av in = gnd or v cc , dip pins 1-6, 9, 14-19 io i/o leakage -10.0 10.0 av o = gnd or v cc , dip pins 11-12 iccsb standby power supply - 10 av cc = 5.5v, v in = v cc or gnd, outputs open iccop operating power supply current - 1 ma/mhz v cc = 5.5v, outputs open, note 2 notes: 1. does not apply to iob , resb, or anyrqst. these are strap options and should be held to vcc or gnd. 2. maximum current defined by clk or bclk, whichever has the highest operating frequency capacitance t a = +25 o c symbol parameter typical units test conditions cin input capacitance 10 pf freq = 1mhz, all measurements are referenced to device gnd cout output capacitance 10 pf cio i/o capacitance 15 pf 82C89
353 ac electrical specifications v cc = 5.0v 10%; gnd = 0v: t a = 0 o c to +70 o c (c82C89); t a = -40 o c to +85 o c (i82C89); t a = -55 o c to +125 o c (m82C89) symbol parameter min max unit test conditions (1) tclcl clk cycle period 125 - ns note 3 (2) tclch clk low time 55 - ns note 3 (3) tchcl clk high time 35 - ns note 3 (4) tsvch status active setup 65 tclcl-10 ns note 3 (5) tshcl status inactive setup 50 tclcl-10 ns note 3 (6) thvch status inactive hold 10 - ns note 3 (7) thvcl status active hold 10 - ns note 3 (8) tbysbl busy setup to bclk 20 - ns note 3 (9) tcbsbl cbrq setup to bclk 20 - ns note 3 (10) tblbl bclk cycle time 100 - ns note 3 (11) tbhcl bclk high time 30 0.65 (tblbl) ns note 3 (12) tclll1 lock inactive hold 10 - ns note 3 (13) tclll2 lock active setup 40 - ns note 3 (14) tpnbl bprn to bclk setup time 20 - ns note 3 (15) tclsr1 sysb/resb setup 0 - ns note 3 (16) tclsr2 sysb/resb hold 30 - ns note 3 (17) tivih initialization pulse width 675 - ns note 3 (18) tblbrl bclk to breq delay -35nsnote 3 (19) tblpoh bclk to bpro - 35 ns note 1 and 3 (20) tpnpo bprn to bpro delay - 22 ns note 1 and 3 (21) tblbyl bclk to busy low - 60 ns note 3 (22) tblbyh bclk to busy float - 35 ns note 2 and 3 (23) tclaeh clk to aen high - 65 ns note 3 (24) tblael bclk to aen low - 40 ns note 3 (25) tblcbl bclk to cbrq low - 60 ns note 3 (26) tblcbh bclk to cbrq float - 40 ns note 2 and 3 (27) toloh output rise time - 20 ns from 0.8v to 2.0v, note 4 (28) tohol output fall time - 12 ns from 2.0v to 0.8v, note 4 (29) tilih input rise time - 20 ns from 0.8v to 2.0v (30) tihil input fall time - 20 ns from 2.0v to 0.8v notes: 1. bclk generates the first bpro wherein subsequent bpro changes lower in the chain are generated through bpron. 2. measured at 0.5v above gnd. 3. all ac parameters tested as per ac test load circuits. input rise and fall times are driven at 1ns/v. 4. except busy and cbrq 82C89
354 ac test load circuits busy , cbrq load circuit aen load circuit bpro , breq load circuit note: includes stray and jig capacitance ac testing input, output waveform ac testing: inputs are driven at v ih +0.4v for a logic ?1? and v il -0.4v for a logic ?0?. the clock is driven at v cc -0.4v and 0.4v. tim- ing measurements are made at 1.5v for both a logic ?1? and ?0?. burn-in circuits md82C89 cerdip test point 100pf 102 ? output from device under test 2.5v (note) test point 2.9v 100pf output from device under test 157.2 ? (note) test point 2.9v 100pf output from device under test 249.6 ? (note) 1.5v 1.5v v il -0.4v input v ih +0.4v v ol output v oh 11 12 13 14 15 16 17 18 19 10 9 8 7 6 5 4 3 2 1 20 f7 f13 f14 f12 f0 v cc v cc/2 f8 r2 r2 r2 r2 r2 r1 r1 r1 r2 v cc c1 r2 r2 r2 r2 r2 r2 r1 r1 r1 v cc/2 f11 f10 f9 f0 f5 f6 82C89
355 mr82C89 clcc notes: 1. v cc = 5.5v 0.5v, gnd = 0v 2. v ih = 4.5v 10%, v il = -0.2v to +0.4v 3. components values: r1 = 1.2k ? , 1/4w, 5% r2 = 47k ? , 1/4w, 5% c1 = 0.01 f minimum f0 = 100khz 10% f1 = f0/2 f2 = f1/2. . . . f14 = f13/2 burn-in circuits 4 5 6 7 8 9101112 13 3 2 1 20 19 15 14 18 17 16 r2 r2 r2 r2 r2 f5 f0 f9 f10 f11 f12 r2 f0 r2 v cc r1 r1 r1 v cc/ 2 v cc c1 f13 f7 r 2 f14 r 2 r 2 f6 r 2 r 2 f8 r 1 r 1 r 1 v cc/ 2 82C89
356 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 die characteristics die dimensions: 92.9 x 95.7 x 19 1mils metallization: type: si - al thickness: 11k ? 2k ? glassivation: type: nitrox thickness: 10k ? 2k ? worst case current density: 1.8 x 10 5 a/cm 2 metallization mask layout 82C89 clk lock crqlck anyrqst sysb/resb iob s2 v cc s1 s0 anyrqst bpro bprn gnd busy cbrq aen resb bclk init breq 82C89

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